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Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis

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In this paper, we propose a latency-constrained scheduling algorithm that minimizes the leakage energy of high-level synthesis designs per computation performed (total leakage energy), by coexploring unit-time leakage power (leakage energy per control step) and latency spaces in order to minimize their product while satisfying a latency constraint. Our exploration of the dimension of latency (within an upper-bound constraint) is orthogonal to other low-power approaches like multiVdd and multi-V th assignments (module selection) of functional units, dynamic power optimization via switching probability reduction, and clock/power gating. It can thus be combined with any or a combination of these techniques to yield lower computation leakage energy than the combination of the corresponding techniques alone. We use the basic premise of the well-known force-directed scheduling (FDS) algorithm of a distribution graph of probabilistic operation scheduling that we view as global probability map of all scheduling possibilities and their probabilistic effects on the metric of interest (number of functional units in FDS, and leakage power in our case) in our algorithm. However, we extend FDS significantly by replacing the uniform scheduling probabilities and force formulation of FDS by: (a) an initial probabilistic distribution graph of the number of functional units used in each control step based on a first-pass non-uniform probability driven randomized scheduling that yields the final starting probabilities that are conducive to leakage energy minimization; (b) a root-mean-square based estimation of the maximum functional unit usage distributed across control steps that contributes to minimizing either the overall unit-time leakage power or total leakage energy; and (c) a fast greedy noncommittal scheduling algorithm for the purpose of estimating the latency for scheduling output operations in order to minimize the product of estimated unit-time leakage power and estimated latency. Experimental results on 11 media benchmarks demonstrate a total leakage energy reduction of up to 64% and an average of 44% compared to conventional FDS with a power-driven modification that only minimizes unit-time leakage power (which is also what other low-power approaches do), and a total leakage energy reduction of up to 39% and an average of 12% compared to a version of our algorithm that has the aforementioned augmentations (a) and (b), but does not explore the latency space for total leakage energy minimization. This demonstrates the efficacy of co-exploring unit-time leakage power and latency spaces for leakage energy minimization.

Keywords: ENERGY OPTIMIZATION; HIGH-LEVEL SYNTHESIS; LATENCY; LEAKAGE ENERGY; SCHEDULING

Document Type: Research Article

Publication date: 01 December 2016

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  • The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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