Design and Verification of Analog CMOS Circuits Using the g m/I D-Method with Age-Dependent Degradation Effects
In this paper a tool based on the g
m/I
D-method is presented to provide information on operating point dependent degradation in integrated circuits. The advantage of the presented GMID-Tool is that neither further SPICE nor ageing simulations are required
since the fresh and aged small signal parameters of a single transistor are extracted at once. Using the GMID-Tool, the design time of an integrated circuit is reduced significantly. Additionally, the GMID-Tool is process-independent and universally applicable as it takes technology specific
data as input. The verification of the GMID-Tool is shown at the example of a Common Source Amplifier and a Miller-OTA.
Keywords: AGE-DEPENDENT; AGING AWARE DESIGN; BIAS TEMPERATURE INSTABILITY (BTI); CIRCUIT DESIGN; CMOS; DEGRADATION; DESIGN; GM/ID-METHOD; GMID-TOOL; HOT CARRIER DEGRADATION (HCI); PROCESS VARIATION; RELIABILITY; TRANSCONDUCTANCE EFFICIENCY; VERIFICATION
Document Type: Research Article
Publication date: 01 March 2017
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