Recent Advances in Low Power Asynchronous Circuit Design

Reducing the power consumption of modern digital CMOS integrated circuits (ICs) is one of the most critical design considerations. The prevailing synchronous ICs use global clocks to control the circuit operation, which causes a substantial amount of power consumed by the clock tree, as well as a series of timing issues that limit the effectiveness of many power reduction techniques. Asynchronous circuits, especially quasi-delay-insensitive (QDI) asynchronous circuits, use local handshaking protocols in lieu of clocks to coordinate circuit behavior. The delay insensitivity and other unique features of QDI circuits allow for more aggressive supply voltage scaling, implementing power gating without timing analysis or extra control overhead, connecting multiple components efficiently across a large die, and many other benefits for energy efficiency. This paper summarizes recent advances in low power QDI asynchronous circuit design, the status of EDA tool support, and some industry practices. In conclusion, while QDI asynchronous circuits have significant power saving potentials in many applications, efforts from researchers, designers, and EDA tool developers are needed to identify these applications, demonstrate the power advantage of QDI circuits, and alleviate the learning curve in automated QDI circuit design, in order for the semiconductor IC industry to more widely adopt QDI asynchronous logic in their products.