Low-Power Coding: Trends and New Challenges

During the last two decades, the advent of very deep sub-micron and nanometric technologies has increased the criticality of the on-chip interconnect architecture. Today, interconnects are affecting the overall chip power consumption, performance and reliability so severely that they need to be optimized at all the abstraction levels. This work discusses the use of coding strategies to reduce the energy consumption and improve the performance of on-chip interconnects. Although there are notable examples of the radical improvements in the communication architecture through coding, the appearance of new technologies and more complex systems is raising important challenges in the field. In this context, the aim of our manuscript is double: first, to provide a review of the existing coding techniques in the literature; and second, to provide a set of challenging problems, whose solution has the potential to advance significantly the current state of the art. When possible, we survey promising approaches to tackle those problems.