Digital Filtering Using Multipliers on Intelligence Extraction and Power-Line Removal from Electromyogram Signals

In recent years, in the era of Very Large Scale Integration (VLSI) domain, full-custom layout designs, Intellectual Property (IP) cores, Silicon on Chip (SoC) designs, and the Field Programmable Gate Array (FPGA) based designs play a vital role in almost all filed of science and engineering. Especially, complementary metal oxide semiconductor (CMOS) Integrated Circuits (ICs) do involve in the design of ultra-low-power biomedical implantable devices. In this study, multipliers which are essential parts in the digital filter are demonstrated using the conventional and pipelined approaches. The 8-bit × 8-bit, 16-bit × 16-bit and 32-bit × 32-bit Wallace tree multipliers are implemented on an Altera FPGA EP4CEF29C7 device using Quartus II 13.1 synthesis software tool and the simulation results on device utilization reports, the speed and the power are obtained. On the digital filtering using multipliers part, the electromyogram signal—the electrical activity of muscles—is used for the experimental purpose. The band-pass filter is used to extract the useful information from the EMG signal, and a notch filter is used to remove the power-line interference portion using different filters. Matlab 9.4 (R2018a) simulation was used to carry out all the EMG filtering experiments.