Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows design of power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows reducing average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.