Compact and Secured Primitives for the Design of Asynchronous Circuits
This paper aims at introducing a novel design methodology of compact, high performance and secured dual rail primitives widely used in quasi-delay insensitive circuits. An example of application of this design methodology to basic quasi-delay insensitive primitives is given on a 130 nm process. The performance and the security properties of the resulting cells are then compared, using electrical simulations, to the implementations proposed in former works.
Keywords: ASYNCHRONOUS; COUNTERMEASURES; DIFFERENTIAL POWER ANALYSIS; QUASI-DELAY-INSENSITIVE; SIDE-CHANNEL ATTACKS
Document Type: Research Article
Publication date: 01 April 2005
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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