Low Power Test Generation for Path Delay Faults

We propose an implicit test pattern generation method for path delay faults that guarantees high fault coverage such that the power dissipated by the generated test pair of patterns satisfy a given threshold. A timed mixed-mode ATPG that combines function-based and structural (PODEM-like) methods is used for faster and accurate test generation. The power dissipated due to the switching between successive pairs of patterns, is also reduced by incorporating stability functions in the mixed-mode ATPG. Typical delay values are considered from an accurate gate delay model. Data structures like Binary Decision Diagrams and Zero Suppressed Binary Decision Diagrams are used to store and manipulate the test functions and path delay faults respectively. The strength of the proposed method is demonstrated experimentally using some sample benchmark circuits.