Leakage and Leakage Sensitivity Computation for Combinational Circuits

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate total system power. Motivated by the need for accurate estimation of the leakage power, in this paper we describe a static (i.e., input-independent) technique for efficient and accurate leakage estimation of combinational logic circuits. Our method is based on a probabilistic method that is used to compute the average leakage of combinational circuits. Furthermore, we also observe that the input dependency of leakage for large combinational circuits is often small due to an averaging effect. The proposed technique gives very accurate estimation results with an average error of only a few percent for the ISCAS circuit benchmarks. We also extend the proposed technique to predict the leakage power components separately, namely the subthreshold and gate leakage components of the circuit. Moreover, the leakage sensitivities of the circuit with respect to environmental and process variables can be also predicted using the proposed method. We demonstrate the application of the sensitivities predicted in developing simple and efficient compact leakage models. The leakage sensitivities can also be use in a wide range of applications including performance optimization, manufacturing yield improvement and product quality enhancement.