High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits

This paper presents a power estimation and optimization methodology in the early stage of high-level synthesis for unscheduled data-dominated circuits. Leakage and dynamic power consumption for a module library are estimated using an automatic construction of switching tables and acquisition of input data statistics. The data profiles are explored to control both dynamic power and leakage power consumption. Dual threshold voltage (V_th) techniques are also utilized to reduce leakage power and energy consumption. Experiments are performed on a data-dominated test suite of 6 benchmarks for two technology generations, 180 nm and 45 nm. The results show that the leakage power will occupy a large part of the total power consumption in the future. For the future technology generation, our optimization technique achieves an average of 25.0% leakage power reduction and 10.5% total power reduction. With the assistance of a dual-V_th library, our technique achieves an average of 82.6% reduction for leakage power, and 40.2% reduction for the total power consumption.