A Load-Store Queue Design Based on Predictive State Filtering
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. Furthermore, the load-store queue is a critical component in terms of scalability. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 40% in the LSQ and 2.5% in the whole processor), and only incurs a negligible performance loss of 1%.
Keywords: DEPENDENCE PREDICTION; LOAD-STORE QUEUE; MICROARCHITECTURE POWER AWARE DESIGN; STATE FILTERING
Document Type: Research Article
Publication date: 01 April 2006
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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