Back-Annotation in High-Speed Asynchronous Design
This paper presents the next step in an evolving back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools. This paper demonstrates that these cells can be efficiently modeled in Verilog, effectively characterized in the standard Liberty format, and support accurate Verilog back-annotation using the standard-delay-format (SDF) flow, thereby enabling digital simulation-based performance and timing verification. Experimental results on several test designs including a 260K transistor parallel prefix 64-bit adder design demonstrate the proposed back-annotation flow yields less than 5% error compared with much more time-consuming analog-level simulation using a circuit simulator.
Keywords: ASIC DESIGN FLOW; BACK ANNOTATION; HIGH-SPEED ASYNCHRONOUS DESIGN
Document Type: Research Article
Publication date: 01 April 2006
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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