Transistor Sizing of Logic Gates to Maximize Input Delay Variability

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay (VID) gate and the maximum difference in delays of any two paths through the gate is known as "u_b." The VID gates have a known application in minimizing the active power of a digital CMOS circuit. A previous publication has proposed three different designs for implementing VID gates. In this paper, we describe transistor sizing methods to implement the three types of VID gates for any specified delay requirement. We also describe techniques for calculating the u_b for each type of gate design. We outline an algorithm for an efficient determination of the transistor sizes for a gate for given delays and output load capacitance. The algorithm is a two-step approach with a look-up table of sizes in the first stage and a sensitivity based steepest descent method for the second stage. We also give a brief introduction to the power saving potential by maximizing u_b when used in conjunction with the previously published technique.