Power Optimized Design of CMOS Programmable Gain Amplifiers

In this paper, we present architectural and circuit level power optimization techniques in the design of CMOS Programmable Gain Amplifiers (PGA). In the realization of PGAs, transresistance amplifiers with resistive feedback are shown to be a more power efficient architectural choice as compared to popular realizations using operational amplifiers and source degenerated amplifiers. A CMOS realization of a fully differential transresistance amplifier employing cascode regulation for low input impedance is described. An inversion coefficient based circuit design methodology is used to select the sizing and bias of transistors in the optimum power-performance region of operation. A figure of merit that enables comparisons of different PGA architectures is also introduced. A combination of simulation and experimental results from 0.5-m CMOS realizations validate the proposed design techniques.