Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, and Threshold Voltage Selection

This paper proposes a novel methodology for statistical leakage minimization of digital circuits. A function of mean and variance of the circuit leakage is minimized with constraint on α-percentile of the path delays using physical delay models fitted to a 90-nm industrial technology. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables can provide significant amount of power savings. The formulated leakage minimization problem is shown to be a multivariable convex optimization problem under specific variable transformations. We demonstrate that our statistical optimization can lead to more than 50% reduction in the 90-percentile leakage for a 6% increase in the required time constraint.