Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power

Traditional monolithic system-on-chip designs are challenged by worsening global interconnections and rising fabrication costs. As an emerging technology, 3-D IC integration offers an appealing solution for significant reduction of the global wire length through multiple vertically stacked active device layers. Furthermore, this new system integration paradigm allows us to combine technologies optimized for different functionalities, and hence opens up new avenues for cost-effective System-On-Chips designs. However, heat removal in 3-D ICs will likely exacerbate and pose a greater challenge in thermal management, control of leakage power, and temperature induced timing and reliability issues must be addressed in realization of such systems. In this paper, a temperature-aware floorplanner for 3-D ICs is presented where the important interdependency between temperature and leakage power is taken into account by developing efficient physical design optimization algorithms in conjunction with effective full-system thermal and leakage modeling, 3-D chip floorplan can be optimized efficiently while simultaneously minimizing area, wire length, maximum temperature, and temperature gradient. Our experiments show that the presented floorplanner is capable of reducing the maximum system temperature and temperature gradient up to at the cost of a mild increase in design area and wire length.