Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power

Static random access memories comprise an increasing portion of modern integrated circuits implemented in CMOS technologies. Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. Additionally, two other seven transistor SRAM cells with similar characteristics are presented. These cells improve the write margin over the proposed six transistor SRAM cell. The cell circuit topologies, layout, and impact on memory design are described. The cells are slightly larger than the conventional SRAM cell, increasing the size by about 11%. Simulation on foundry 130 and 90 nm technologies and with predictive technology models for 65 and 45 nm technologies demonstrate the leakage reduction and performance.