Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption

This paper proposes a novel methodology for optimization of the total power consumption (static plus dynamic) of a combinational circuit under delay constraints. First, a unique matrix representation of the circuit topology is developed to capture the circuit delay constraints. The representation is then used to develop an optimization scheme that proceeds by varying the delay-assignments of the various gates in the circuit and searching for the assignment with minimum energy consumption. The novel matrix representation is used to derive an exact mathematical condition on the supply and threshold voltages of modules in a combinational circuit that minimizes total power consumption under a delay constraint. Ametric is developed that can be used by circuit designers to test how close their design is to the point of optimum power consumption. To enable application of the optimization scheme on CMOS combinational circuits with a large number of gates, a hierarchical application of the scheme is presented for determining the optimal sizes, supply and threshold voltages for the gates such that the overall energy consumption of the circuit is minimized for the given delay constraint. The proposed method yielded energy savings of 35.9% on average on un-optimized ISCAS'85 benchmark circuits while incurring a negligible delay penalty. Compared to traditional zero-slack methods, the method yielded 12% additional energy savings on average.