Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing

This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transitions are minimized. In addition, scan cells in segments of the same weight are reordered to further reduce the scan-out transitions. Experiments on ISCAS circuits show that, compared with the pseudo random BIST, SWR-BIST effectively reduces the test power by 74%. The SWR-BIST circuitry is very small and it grows slowly with the CUT size. The penalty of this technique is area and routing overhead for scan chain reordering. The SWR-BIST has been implemented on a real communication chip and the measurement data confirm the effectiveness of the proposed SWR-BIST.