Lethargic Cache: A Low Leakage Direct Mapped Cache
This paper proposes special level-1 cache scheme that greatly decreases the growing leakage power proliferation in short channel cache memories based on gated supply voltage mechanism (gated-Vdd), a commonly-known circuit technique used to control power supply to cache cells. The proposed scheme slashes 26% of the total leakage dissipated in a conventional baseline at the cost of marginal performance degradation and silicon die area.
Keywords: AVERAGE MEMORY ACCESS TIME (AMAT); CACHE LINE INDEX; GATED VDD; STACKING EFFECT; VERY DEEP SUBMICRON (VDSM); VIRTUAL GROUND
Document Type: Research Article
Publication date: 01 August 2007
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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