Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems
Power estimation techniques able to handle high levels of abstraction are strongly required to face up the increasing complexity and the stringent power budgets of current designs. This work addresses the modeling of signal activity and inter-wire coupling effects in data-intensive linear DSP architectures that share one or more resources. In this context, a rigorous mathematical model for the evaluation of those metrics is described. Furthermore, as a practical evaluation of the proposed technique, the work addresses the problem of power-aware binding during high-level synthesis. Experimental results show that the proposed estimation technique provides an excellent accuracy with errors smaller than 10% and a reduction in estimation time of two orders of magnitude respect two simulative approaches.
Keywords: HIGH-LEVEL SYNTHESIS; INTER-WIRE CAPACITANCE; LOW POWER BINDING; POWER ESTIMATION; TRANSITION ACTIVITY
Document Type: Research Article
Publication date: 01 August 2007
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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