Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications

Specification of a concurrent system using CAOS (Concurrent Action Oriented Specifications) (CAOS) as illustrated by Bluespec Inc.'s Bluespec System Verilog provides a high abstraction level, effective concurrency management through atomicity, and powerful compilation to efficient RTL hardware. In this paper, we present two algorithms that make CAOS to RTL synthesis power-aware and produce RTL that can be synthesized into hardware competitive in terms of power/area/slack trade-off against the well-known industrial-strength power optimization RTL to gate-level synthesis tools. Our algorithms are simple and intuitive because the higher abstraction level allows one to easily analyze certain exploits that exist in the model. Discovering these opportunities at the RTL and lower levels require a much more involved circuit or gate structure analysis. We show through extensive experimental results that when a CAOS specification is compiled using our algorithms, the resulting hardware (without any additional gate-level power optimizations) has power/area/latency numbers comparable to those obtained by using existing tools for applying gate-level power minimization techniques. Also, the experiments show that in the absence of gate-level power optimizers such as Magma Blast Power or Synopsys Power Compiler, these algorithms show significant power reduction over standard Bluespec Compiler (BSC) for CAOS to RTL generation. And most importantly, our algorithms allow analyzing the affects of various power saving techniques in the early phases of the design cycle, thus avoiding the need to perform logic synthesis for such an analysis.