Timing-Aware Power Minimization via Extended Timing Graph Methods

With the advancement of multiple threshold devices, leakage power can be better controlled, utilizing fast and high-leakage devices just for critical paths, while low-leakage devices are used for non-critical parts to minimize power. In this paper, a practical timing graph-based algorithm is proposed to perform concurrent discrete optimization (V_t-assignment, device width biasing, device length biasing, etc.) to minimize the power consumption, especially leakage, of a circuit subject to timing performance constraints. Our algorithm honors important constraints that are common to an industrial design methodology, including hierarchy, structural connectivity and layout-related rules. We demonstrate the performance of the algorithm in an industrial design automation platform consisting of an incremental transistor-level timing analysis engine and optimization environment.