Low Power and Energy Efficient Asynchronous Design
This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip.
Keywords: ASYNCHRONOUS DESIGN; ASYNCHRONOUS NOC; DYNAMIC VOLTAGE SCALING; ENERGY-EFFICIENCY; GALS; LATCH-BASED DESIGN; LOW-POWER; PERFECT CLOCK GATING; SUBTHRESHOLD DESIGN
Document Type: Research Article
Publication date: 01 December 2007
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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