Architectural Power Analysis for Intellectual Property-Based Digital System

The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modelling technique at architectural level for the digital electronic systems composed of IP components by using the statistical knowledge of their primary inputs/outputs. During the characterization process, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate the power dissipation of the system just by using the statistics of the IPs primary inputs/outputs. In our experiments with the test IP system, the average error is 26%.