Test Power Analysis at Register Transfer Level
This paper presents a new solution which allows the analysis of test power early in the design process. The solution is structured on existing design tools and bring new capabilities in qualifying an RTL design as “test power” compliant or not. By using typical test case it is shown how much the association between existing design tools and a new technology which inserts DFT at RTL augments existing design flows and helps in pinpointing and correcting test power problems.
Keywords: ATPG; PEAK AND AVERAGE POWER; RTL DESIGN FOR TEST; TEST POWER ANALYSIS
Document Type: Research Article
Publication date: 01 December 2008
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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