A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing

We propose a parallel and randomized algorithm to solve the problem of discrete Dual-Vt assignment combined with continuous gate sizing which is an important low power design technique in high performance domains. This combinatorial optimization problem is particularly difficult to solve on large-sized circuits. In this paper, we first introduce a novel hybrid algorithm which combines the existing heuristics and convex formulations for this problem. Consequently the hybrid algorithm can achieve a better way to explore the tradeoff between the runtime of the algorithm and the quality of generated solution (i.e., total power). Next, we extend our hybrid algorithm to include parallelism and randomization. We introduce a unique utilization of parallelism to better identify the optimization direction. Consequently, we can reduce both the number of iterations in optimization as well as improve the quality of solution. We further use random sampling to improve the already-obtained solution so that the optimization effort is indeed focused on the more "promising" regions of the solution space. For this combinatorial optimization problem, our algorithm can improve the average total power by 34% compared to the state of the art which is based on solving a continuous convex program and applying discretization. Our power improvement is over 48% for the larger benchmarks, featuring over 40,000 gates. In addition, our algorithm is faster than solving the continuous convex program. This is for an implementation on a grid of 9 machines.