Selective Forward Body Bias for High Speed and Low Power SRAMs

Leakage power consumption is a large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large fraction of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45 nm technology node, since these processes have significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from a performance degradation standpoint. In this paper, we quantify this problem and provide a solution, using a 45 nm 512 KByte SRAM as a design example. We show that implementing the SRAM as a monolithic memory results in increased delay as well as power. We illustrate a methodology to optimally reduce leakage power and improve performance in memories by splitting the memory array into word line groups (WLGs) and forward body bias a WLG selectively when it is accessed. We present a derivation of optimal number of WLGs and the forward body bias voltage value, and show that our approach results in a 9.2% access time reduction, and a 53.4% reduction in power during a read operation. Our approach also achieves an 18% reduction in power during a write operation and a 69% leakage power improvement. The area overhead of our scheme is 7.2% compared to a monolithic memory. Our approach does not compromise on the static noise margin (SNM). From an architectural standpoint, we also present a strategy to decide when a WLG should be left forward biased between non-successive accesses, in order to minimize the total power consumption of memory.