A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks
In wireless sensor network applications, autonomy is a critical feature. So, a new design method under power consumption constraint, dedicated to inductively degenerated Low-Noise Amplifier, is proposed in this article. A detailed analysis of power consumption, gain, noise and linearity performances of this topology is performed. The simulation results using MATLAB show the impact of each MOSFET dimensions into Low-Noise Amplifier performances. Based on these results, a new method to design Low-Noise Amplifier is proposed using an example. A 868-MHz Low-Noise Amplifier is then designed in CMOS 0.35 m technology to validate our method. Considering the literature, measurement results show good characteristics: 13 dB gain, 1.5 dB Noise Figure with an ultra low-power consumption of 6.7 mW at supply voltage of 2 V.
Keywords: AUTONOMY; POWER CONSTRAINED LOW-NOISE AMPLIFIER; WIRELESS SENSOR NETWORKS
Document Type: Research Article
Publication date: 01 August 2009
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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