Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology

This paper reports on the systematic analysis of impact of biasing the transistors in subthreshold versus saturation conditions on analog circuit performance. A cascode current mirror, designed in 130 nm CMOS technology, is biased in subthreshold and saturation regions and its performance has been analyzed through rigorous analytical modeling. The analytical results have been validated with SPICE simulations. We demonstrate that the subthreshold operation provides better performance in terms of linearity, power, area, output impedance and tolerance to temperature variation, making it a preferable option for applications such as signal conditioning circuitry for environmental sensors. On the other hand, biasing the circuit in saturation is preferable for applications like transceivers and data converters where high bandwidth, SNR and low sensitivity to process variations are the key requirements. Based on this analysis, we have prototyped a sensor interface circuit for resistance measurement on 130 nm CMOS technology, using subthreshold cascode current mirrors as the key building blocks. This current mirror results in 14 × lower power compared to above-threshold operation. The interface circuit spans 5 orders of magnitude of resistance, and consumes an ultra low power of 326 W.