Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs

Recent advances in subthreshold logic design methodologies and strategies show their potential for future ultra low power applications. Although DGFinFETs have shown to be better candidates for subthreshold logic design than equivalent bulk CMOS devices, there is not much effort to find optimal configuration of DGFinFETs, i.e., symmetric, asymmetric, tied gate, independent gate options for robust and energy efficient subthreshold logic design. In this paper, the performance and robustness comparative studies of basic subthreshold logic gates and combinational circuits such as full adder, multiplexers etc., constructed with all possible DGFinFET device options have been done. We also investigate their behavior with and without the presence of process variations. PVT variations implications at circuit level in terms of SNM and standby power degradation also have been shown for better robustness comparisons. Comparison of various circuit styles in combination with DGFinFET options for optimal subthreshold logic also has been done. We conclude that tied gate device option with asymmetric feature shows to be better option for energy efficient subthreshold logic design, and independent gate device option with asymmetric option shows to be better option for robust subthreshold logic design. Independent device gate option (4TSDG) is ≈65% more robust than tied gate device option (3TSDG) for symmetric case, and ≈75% more robust for asymmetric case for subthreshold logic. 4TADG shows to be ≈26% more robust than 4TSDG device option for subthreshold logic.