A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure

Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occurs within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. We then propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). Using SCAP model provides a cost-effective solution to identify patterns with high IR-drop and avoids expensive dynamic IR-drop analysis. A new practical pattern generation procedure is proposed to generate supply-noise tolerant delay test patterns. The results demonstrate that the new pattern set, while slightly larger, will minimize the supply noise effects on path delay.