Power-Yield Enhancement for Field Programmable Gate Arrays Under Process Variations

Leakage power is a paramount concern in the design of Field Programmable Gate Arrays (FPGAs), and process variations have aggravated the problem. At the 45 nm technology node and beyond leakage variations can diminish the power yield of a design. To handle the increased complexity of the state-of-the-art designs, FPGAs have been scaled in size and complexity, leading to increased leakage, and more variation in leakage power. In this paper impact of process variations on the leakage in FPGAs is analyzed and variability aware CAD algorithms for mitigating the impact of process variations are developed. A programmable dual-Vdd FPGA architecture is selected on which these algorithms are implemented to evaluate the improvement in the power yield of FPGAs. The results indicate that the proposed CAD technique leads to 3%–9% improvement in the power yield.