Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits

In this paper, we characterize the Energy-Delay performance of logic circuits realized using Single Electron Transistor (SET) devices. As technology scaling progresses, it is getting increasingly challenging to continue reducing energy, especially at low activity factors and low V_CC, due to increasing leakage energy dominance. A SET can be viewed as the ultimate transistor operating in the limit of scaling; hence, we use this device as an example to understand the challenges of energy-reduction in the nanoscale. We explore the design space for SET-devices based on physical dimensions and electrostatic properties. Based on this design space, we characterize SETs into categories of applications: complementary-logic design, and BDD design with sense amplification. Based on these two circuit design styles, we compare the Energy-Delay products of benchmark logic circuits, implemented using nanometer CMOS and SETs.