Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing

In this paper, we propose a process-variation-resistant logic design method. We show that in the logic circuits working at sub-nominal supply voltage (V_DD), proper selection of the logic architecture and V_DD together, can reduce the impact of the intra-die and inter-die variability on the timing significantly. First we show that / ratio of the transistor current and delay strongly depends on the V_DD. Then, we compare the Process Variation (PV) sensitivity of Low-Power Slow (LP-S) architectures with High-Power Fast (HP-F) ones. The results show that for a given technology, equal power budget, and equal delay, LP-S circuits working at a higher V_DD are less PV sensitive compared with HP-F circuits working at a lower V_DD. Our method is particularly useful for combating intra-die random variability.