Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies

Sub-threshold circuits have emerged as a strong candidate for use in future energy-constrained applications. In a non-homogeneous design paradigm that contains high power-density superthreshold blocks abutting sub-threshold blocks, it becomes imperative to examine the effects of a variable ambient temperature on sub-threshold circuit operation. Unlike super-threshold, the sub-threshold I _ON increases exponentially with temperature but the I _ON-to-I _OFF ratio degrades by 0.52%/°C in 45 nm technology due to an increase in inverse sub-threshold slope (S) values with temperature. Temperature as an environmental variable presents 2 design-corners in sub-threshold: (1) very low temperatures of operation (≤–25°C) could affect the timing-yield since the circuits become slower and the delay-sensitivity to process-variations also increases manifold and (2) very high temperatures of operation (≥125°C) could potentially affect the functional yield since the Static Noise Margin (SNM) values degrade significantly. The total energy consumed also increases significantly due to a tremendous increase in the relative contribution of E _leak at higher temperatures. Although performance is a secondary design objective in sub-threshold, it is extremely necessary that the circuits satisfy timing constraints imposed by the worst-case process and operating corners. To incorporate the effect of temperature on timing-yield of sub-threshold circuits, we propose 2 metrics to describe the practical-energy consumption: T_Induced_E _maxTcycle and PT_Induced_E _{worst-caseTcycle} which are the energy consumed per cycle for temperature induced maximum cycle-time and process and temperature induced worst-case cycle-time respectively. The practical energy values are >10× greater than E _nom/cycle and exhibit significant temperature dependence causing the V _DDmin (supply yielding minimum energy) to be pushed to a much higher value for a higher temperature of operation. Using these metrics, we study the temperature effects on the design-space in terms of the different circuit-design choices: gate-sizing, fan-out per gate and logic-depth. From the timing-variability perspective, long-paths constructed using low fan-out, upsized gates represent the best-case. For a circuit of the same topology (gate-arrangement, logic-depth and fan-out), the practical energy values increase as gates in the circuit are uniformly upsized. To evaluate the relative trade-off between energy-consumption and process-robustness under the combined effects of process-variations and thermal stress, we use a metric called Practical-Energy-Variability-Product (PEVP) which is the product of PT_Induced_E _{worst-caseTcycle} and the coefficient of variability of T _cycle under current operating conditions. Paths which simultaneously minimize timing-variability, satisfy worst-case cycle-times and optimize the total energy consumed are those constructed using minimum sized gates in spite of their much higher vulnerability to process-variations. The results obtained are for circuits with >99.9% timing yield and having a relatively high and pessimistic supply-voltage of 350 mV. Allowing scope for supply-tuning while ensuring >99.9% functional yield we found that the PEVP values can be reduced by ≥75% across the design-space for different circuit topologies.