Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test

Scan compression techniques are widely used to contain test application time and test data volume. Smart techniques exist to match the scan compression CoDec (compactor-decompressor) module with the DUT (design under test), to realize high levels of compression with no loss of coverage. DUT partitioning is often desirable for ease of implementing sub-chips and integrating them into an SOC (system-on-chip). This paper presents various multi-CoDec configurations for partitioned DUTs to enable efficient scan testing, which address the requirements of reduced test mode power with no compromise in test quality. Different configurations are examined, tradeoffs discussed, and the most suitable one amongst them identified. It is shown how the preferred configuration can be architected with low implementation overhead (with no new requirements for bounding when creating the individual partitions), and how the different CoDecs—DUT partitions can be operated together to meet dual goals of high quality and low power, with no increase in test time. Experimental data is presented on industrial circuits to illustrate the benefits.