Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications

In this paper, analytical models for timing analysis of a complementary metal-oxide semiconductor buffer driven resistance-inductance-capacitance interconnect load in sub-threshold regime of operation have been proposed. Closed form expressions are given for estimating the output voltage and propagation delay. Analytical model is also provided for resistive current and power estimation. It is shown that operating transistor in the sub-threshold region leads to an order of saving in power dissipation in comparison to normal strong inversion. Therefore, sub-threshold regime is highly suitable for ultra low power circuit design. The analysis has been carried out for three technology nodes viz. 130 nm, 90 nm and 65 nm. The results are verified using SPICE simulations. A good agreement is found between the analytical and the simulation results.