Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below
In this paper, we present the comparison of Silicon on Insulator (SOI) Ultra-Thin Body and Buried Oxide (UTBB) substrates with two different back planes (BP) designed to address Low Leakage (LL) and High Speed (HS) Static Random-Access Memory (SRAM) bitcells. The power management capability
is analyzed for both n- and p-type BP. We demonstrate that the back biasing does not induce any degradation of the V
T variability (maintained at A
VT = 1.4 mV ยท μm) on each BP and enables improving the I
SAT/I
OFF
characteristics. This excellent variability is transferred in SRAM Noise Margin (SNM) in read mode where low minimum operating supply voltages (V
MIN) below 0.6 V are demonstrated. Thanks to the back biasing, it is possible to achieve 26% bitcell read current (I
CELL)
improvement with 6% standby leakage current (I
SB) reduction when the substrate voltage (V
B) is equal to 0.9 V (on a p-type BP). Finally, due to low σ
SNM and large μ
SNM changes with V
B,
the SNM/σ
SNM ratio (and thus V
MIN) can be optimized, up to a factor of 30% and 68% when V
B = –0.9 V, respectively for p- and n-type BP.
Keywords: 6T-SRAMS; FDSOI; STATIC NOISE MARGIN; THRESHOLD VOLTAGE VARIABILITY
Document Type: Research Article
Publication date: 01 February 2012
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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