Impact of Power Consumption and Temperature on Processor Lifetime Reliability

A single chip or a system can have more than billion transistors, and billions of vias connected through miles of interconnections. This paper aims at analyzing hard errors, such as, electromigration, hot carrier injection and others at functional level and to estimate the accuracy of the reliability aware ArchC based processor simulator using state of the art power and temperature simulators. We use this reliability simulator to provide the cumulative failure rate for a processor simulated at functional level, at 373 MHz and 1.21 V. The simulations are assumed to be under consideration of ideal environment, with no humidity and no variability.