Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC–DC Converter

In this paper, we propose an embedded switched capacitor based DC–DC converter with high power efficiency and high power density. The converter consists of an array of cross-coupled elements rotationally controlled with non-overlapped interleaved signals. The cross-coupled switched capacitor helps to reduce switching losses. The clock signals help to eliminate shoot through current and reduce ripple. The other contribution is that the converter is integrated with frequency regulation loop, thus adjusting the switching losses according to load and improving the efficiency over a wide range of load current. Further, with the incorporation of the dynamic leaker, the response of the converter is improved under fast transients. The converter is designed in 0.18 μm CMOS technology. The output voltage is adjustable in the range of 1.3 v–1.6 v from the input voltage of 3.3 v. The silicon characterization of the converter gave the measured data consistent with the simulated results. The peak power efficiency of the converter for the unregulated and regulated output are 87% and 75% respectively, while the output ripple is below 30 mV. The output current driving capability of the converter is upto 26 mA with the 490 pF embedded capacitor (including load capacitor). With the help of push-pull dynamic leaker circuit, the dips and peaks due to a load transient are reduced in addition, settling time is also improved. The power density of the converter is 0.45 Watt/mm².