An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together

Partitioning is an effective method for synthesis of low power finite state machines (FSM). To make the partitioning more effective power gating can be applied to turn OFF the inactive subFSM. During transition from the states of one subFSM to the states of other subFSM, the supply voltage is required to be turned OFF for one subFSM and turned ON for other subFSM. This adjustment of supply voltage needs some amount of time, called wakeup time which affects the partitioning of FSMs for its power gated implementation as both the subFSMs are ON during this time. In this paper we have considered this issue by developing a new probabilistic power model of the power-gated design of FSM and finding the boundary depth. As effective partitioning and encoding of FSM decides the power consumption of final power gating implementation, in this paper Genetic Algorithm (GA) has been used to solve this integrated problem of both bi-partitioning and encoding. Experimental results obtained show the effectiveness of the approach in terms of total dynamic power consumption, compared to the technique reported in the literature. Power has been estimated at 45 nm technology and variation of power consumption for different boundary depth has been shown. Affects of the size of sleep transistor and subFSM on the boundary depth have also been studied. Power gated area, reported in this paper is not so high.