A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing

A semi-analytical approach is proposed to calculate link testing energy consumption of mesh NoC using IEEE JTAG standard. A transistor-level model is presented to calculate dynamic energy and HSPICE simulation is used for static energy. Furthermore, the switching activities and test time are calculated using a special purpose cycle-accurate NoC simulator. The results are integrated into the proposed model to obtain total energy consumption and verified with HSPICE simulation. Using the model, the most energy-consuming parts, power peaks, area overhead, and test time are calculated and identified. As a result the model is useful to study the trade-offs in JTAG test architecture implemented on NoC and optimise it in terms of power, test time and area.