A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices

Power gating is an effective technique to reduce static power consumption in integrated circuits. One of the important challenges in power gating architectures is the wakeup current that results from activating blocks in the design after their idle periods end. This wakeup current, also known as inrush current, may cause malfunction of the design. Although solutions exist in power-gated application-specific integrated circuits (ASICs) for this problem, these solutions are fixed and not suitable for reconfigurable devices such as field-programmable gate arrays (FPGAs). In reconfigurable devices, an application is mapped to the device in the field, which means that there is not enough information about inrush current requirements when the chip is fabricated. In this paper we propose a configurable architecture that limits inrush current in power-gated reconfigurable architectures to a safe level. The proposed architecture is configurable to satisfy the inrush current requirements that different applications may experience during the activation phase of power-gated modules. We investigate the different tradeoffs associated with the proposed architecture. Our results show that the area and power overheads of the proposed inrush current limiting architecture are negligible.