2-Bit Full Adder Implementation Using Single Spin Logic Paradigm
This paper presents the design of 2-bit complementary CMOS Full adder and 2-bit high performance Kogge-Stone Adder using Quantum Dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. On comparing these adders, it was found that, as
in conventional CMOS design, Kogge-Stone Adder computes faster than complementary CMOS Full Adder but occupies larger area.
Keywords: FULL ADDER; QUANTUM DOTS; SINGLE SPIN LOGIC
Document Type: Research Article
Publication date: 01 June 2014
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
- Editorial Board
- Information for Authors
- Subscribe to this Title
- Terms & Conditions
- Ingenta Connect is not responsible for the content or availability of external websites
- Access Key
- Free content
- Partial Free content
- New content
- Open access content
- Partial Open access content
- Subscribed content
- Partial Subscribed content
- Free trial content