Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects

In this paper, a novel voltage mode serial transceiver is proposed for on-chip global interconnects. In order to minimize the power dissipation and to increase the speed, a novel domino logic based multiplexer and an improved voltage mode de-multiplexer cum sense amplifier (IVDSA) are proposed. A modified Delay locked loop (DLL) is also proposed for reducing the jitter as well as the number of clock cycles required for locking. The design of the proposed transmitter and DLL are carried out using method of logical effort. For the purpose of comparison, the transceiver for a Metal 4 interconnect of 5 mm length and 0.6 μm width is implemented in 180 nm technology using the proposed circuits and their performances are compared with that reported in literature. From the post layout simulation results, it is found that the transceiver operates at a speed of 4 Gb/s. The transmitter using domino logic based multiplexer achieves the same speed as that using 4:1 CMOS multiplexer but at 3.25 times lower power dissipation. The power dissipation of IVDSA is 2.88 times lower than that of a voltage mode sense amplifier and its sensitivity and bandwidth are higher by a factor of 10 and 2 respectively. The jitter of the modified DLL is lower by a factor of 1.4 and the locking time is 2 clock cycles less than that reported in literature.