Energy Consumption by Reversible ircuits in the 130 nm and 65 nm Nodes

Previous studies in the CMOS 350 nm technology node, showed that adiabatic dual-line pass-transistor reversible CMOS circuits may be of real interest, especially for human-machine interaction applications such as video, sound and all embedded functions where low-power, low-consumption are mandatory and where frequencies are not the main concern. But the question of viability, suitability and consumption of the quantum-inspired adiabatic reversible CMOS technology with the reduction of the feature size is often asked. With the reduction of transistor sizes, comes an increase of gate leakage that may have a negative impact both on the computation reliability and on the consumption. In another hand, size reduction may allow a gain in performance for an equivalent energy consumption. This paper gives a first evaluation on the consumption by the adiabatic reversible circuit in the 130 nm and 65 nm technology nodes. We show that both 130 nm and 65 nm technologies are suitable for reversible computation. Even better, compared to longer transistor nodes, both small sizes allow to reduce the energy consumption below 1 pJ per transistor and per cycle.