Spatially Distributed Dual-Spacer Null Convention Logic Design
Null convention logic allows designing power, area and speed-efficient asynchronous circuits while maintaining a standard cell-based design flow. This paper proposes a new logic template for null convention logic design. The template relies on the spatial distribution of different spacer
values, using both return-to-one and return-to-zero handshake protocols. In order to compare this template with others, transistor level simulation of a Kogge-Stone adder serves as case study. Simulation results demonstrate that the proposed template allows better energy, static power and
speed tradeoffs while furthering a standard cell-based approach.
Keywords: ASYNCHRONOUS CIRCUITS; FOUR-PHASE PROTOCOL; NULL CONVENTION LOGIC; QUASI-DELAY-INSENSITIVE; RETURN-TO-ONE; RETURN-TO-ZERO
Document Type: Research Article
Publication date: 01 September 2014
- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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