A Novel Low Power Three-Input OR/XNOR Gate Design

Three-input OR/XNOR gate is the basic complex gate for Reed-Muller (RM) logic to implement logic circuits. To overcome the drawbacks of the present OR and XNOR cascaded OR/XNOR gate with the long delay time, high power consumption and power delay product (PDP), a low power three-input OR/XNOR gate at the transistor level is proposed. The proposed design is simulated using Cadence IC5141 and Synopsys HSPICE with 55 nm CMOS process at 1.2 V standard supply voltage. The post-simulation results demonstrate that the proposed circuit has the advantages of low power, fast speed, and low PDP compared with the classical cascaded designs, and the improvement of the power and PDP are up to 21.88% and 38.61%, respectively.