Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET

Simulations of modern nanoscale tunnel devices have theoretically proposed some excellent results. Very recently proposed Si Junctionless Tunnel FET have set a new platform for research where we are able to implement band to band tunneling in a Junctionless silicon body. However, there has been no such work to focus on the impact of defect states on the performance of the device. In this paper, we try to analyze and physically understand how the performance metrics such as subthreshold swing (SS), I _OFF (OFF state leakage current) and mobility are affected by traps. The trends in the transfer characteristics with change in parameter for traps such as trap energy level and density of traps is also understood. With the help of Shockley-Read-Hall recombination model we try to model the effect of trap assisted tunneling. Negative value of the recombination rate suggests higher rate of tunneling due to traps. Added to all of these, we try to observe the impact of temperature on the device current due to the presence of traps.